/* register rename */
module rename (Rs, Rt, Ts, Tt, Rd_en, Rd, Td, Rc_en, Rc, Tc, flush, clock);
	/* NOTE: You may want to add/remove some "reg" denotation, depending
	   on whether you use "always" block or "assign" statement */
    // source renaming
    input[4:0] Rs;			// first source register
    input[4:0] Rt;			// second source register
    output reg[5:0] Ts;		// tag for the first source
    output reg[5:0] Tt;		// tag for the second source

    // dest renaming
	input Rd_en;			// enable dest renaming; from control & allocator
    input[4:0] Rd;			// dest register 
    input[5:0] Td;			// tag for dest, from allocator

    // update on commit
	input Rc_en;			// enable update; from commit logic
    input[4:0] Rc;			// dest register for committed inst
    input[5:0] Tc;			// tag for committed inst

	input flush;			// reset status table
    input clock;			// clock input

    reg[5:0] status[31:0];	// register status table (register alias table)
	integer i;				// need for loop for flushing

	/* Your code */
	
endmodule