CPRE 581 Computer Systems Architecture, Fall 2005

CPRE 581 Computer Systems Architecture

Iowa State University
Fall 2005

COURSE INFORMATION

Meeting: MW 2:10-3:25PM, Howe 1344
Instructor: Zhao Zhang
Office Hours: MW 3:30-4:30PM or by appointment
Office Location: 368 Durham
Contact: phone 294-7940, e-mail: zzhang@iastate.edu
Number of Credits: 3
Prerequisite: CprE 305 Computer Organization and Design or an equivalent course

COURSE DESCRIPTION

Quantitative principles of computer architecture design, instruction set design, processor architecture: pipelining and superscalar design, instruction level parallelism, memory organization: cache and virtual memory systems, multiprocessor architecture, cache coherency, interconnection networks and message routing, I/O devices and peripherals.

TEXTBOOK

J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd edition, Morgan Kaufmann Publishers, Inc., 2002.

REFERENCES

John Paul Shen and Mikko H. Lipasti, Modern Processor Design: Fundamentals of SuperScalar Processors, McGraw Hill, 2002.
D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 2nd Edition, Morgan Kaufmann Publishers, 1997.
Selected papers from journals and major conferences in computer architecture.

COURSE OUTLINE

Introduction
Instruction Set Principles and Examples
Performance Evaluation Methodology
Superscalarprocessor techniques
VLIW and EPIC processors
Memory Hierarchy Design
Storage Systems
Multiprocessor systems
Advanced topics

HOMEWORK ASSIGNMENTS

There will be seven to nine homework assignments. Most problems will fall into one of the following categories:

Conceptual: To review the understanding of a subject.
Analytical and Evaluative: To analyze performance, cost, power or other metrics and to evaluate the merit or weakness of a design, research idea or product.
Problem Solving: To give a design for a problem or to optimize an existing design.
Reading: To answer questions related to reading assignments.
Simulation: To develop simulation modules, run simulation and report results.
Logic Design: To develop the logic design of a hardware component using Verilog.

You must check out assignments and submit your answers on WebCT. Assignments are Microsoft Word files and you must submit your answers in either Microsoft Word or PDF files.

REPORT AND PRESENTATION

Write a survey report on a research topic. A list of suggested topics will be given. On campus students will give a presentation.

EXAM

There will be two exams, mid-term exam and final exam.

CLASS PARTICIPATION

On campus students are expected to attend class meetings and to participate the discussions. Off campus students are expected to participate discussions on class bulletins. Class bulletins are hosted on WebCT.

GRADING

Homework Assignments: 40%
Report and Presentation: 15%
Midterm: 15%
Final: 25%
Class participation: 5%

Students with Disabilities: If you have a disability requiring accommodation in this class, please notify the instructor at the beginning of the semester.