Readings

History and overview

• The IBM 360 Model 91: Processor philosophy and instruction handling" by D. W. Anderson, F. J. Sparacio, and R. M. Toimasulo, IBM Journal of Research and Development, vol. 11, no. 1, January 1967
• "The case for the reduced instruction set computer" by David Patterson and David Ditzel, ACM SIGARCH Computer Architecture News, Vol.8, No.6, October 15, 1980, pp.25--33
• "The future of microprocessors" by Albert Yu, IEEE Micro, December 1996, pages 46-53

Superscalar Implementation and Real Processors

• Complexity-Effective Superscalar Processors, Ph.D. Thesis, S. Palacharla, 1998. (Chapters 1 and 2 are must-read. )
• The Microarchitecture of Superscalar Processors, J. S. Smith and G. S. Sohi, Proceedings of the IEEE, 83:1609--1624, Dec 1995.
• Complexity Effective Superscalar Processors, S. Palacharla, N. P. Jouppi, and J. E. Smith, ISCA'97.
• The MIPS R10000 Superscalar Processor, Kenneth C. Yeager, IEEE Micro, April 1996.
• The Alpha 21264 Microprocessor, R. E. Kessler, IEEE Micro, March 1999.
• The Microarchitecture of the Pentium 4 Processor, G. Hinton et al, Intel Technology Journal Q1, 2001
• The PowerPC 604 RISC Microprocessor, S. P. Song, M. Denman, and J. Chang. IEEE Micro, October 1994.

Precise Interrupt

• Implementing precise interrupts in pipelined processors" by James E. Smith and Andrew R. Pleszkun IEEE Transactions on Computers, 37(5):562--573, May 1988.

Branch Prediction

• J. E. Smith, A study of branch prediction strategies, ISCA'81.
• T. Yeh and Y. N. Patt. Alternative implementations of two-level adaptive branch prediction, ISCA'92.

Cache Organization

• Alan Smith. Cache memories, ACM Computing Surveys, vol. 14, no. 3, 1982. (The most famous paper in cache designs)
• W. H. Wang, J.-L. Baer and H. M. Levy, Organization and performance of a two-level virtual-real cache hierarchy, ISCA'89.
• N. P. Jouppi and S. Wilton, Tradeoffs in two-level on-chip caching, ISCA'94.
• J.-K. Peir, W. W. Hsu and A. J. Smith. Functional implementation techniques for CPU cache memories. IEEE Transaction on Computers, Vol. 48, No. 2, Feb. 1999.

Cache Prefetching

• N. Jouppi. Improving direct-Mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. ISCA 1990.
• S. VanderWeil and D. Lilja. Data prefetch mechanisms. ACM Computing surveys, Vol 22. No. 2, 2000.
• Suleyman Sair, Tim Sherwood, and Brad Calder. A decoupled predictor-directed stream prefetching architecture. IEEE Transactions on Computers, Vol. 52, No. 5, March 2003. First appeared in the proceedings of the 33rd International Symposium on Microarchitecture, December 2000.

Multiprocessor

• A. Agarwal, J. L. Hennessy, R. Simoni, and M. A. Horowitz, "An evaluation of directory schemes for cache coherence", ISCA 1988.
• S. Adve and K. Gharachorllo. "Shared memory consistency model: A tutorial". IEEE Computer, December 1996, pages 66-76. WRL report version.
• Chris Gniady, Babak Falsafi, T. N. Vijaykumar. "Is SC + ILP=RC?" ISCA 1999.

Secure Processor

• B. Yee. Using Secure Coprocessors. PhD thesis, Carnegie Mellon University, May 1994. CiteSeer.
• G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas. Aegis: architecture for tamper-evident and tamper-resistant processing. ICS, pages 160--171. ACM Press, 2003. CiteSeer.
• D. Lie, C. A. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. C. Mitchell, and M. Horowitz. Architectural support for copy and tamper resistant software. In Architectural Support for Programming Languages and Operating Systems, pages 168--177, 2000. CiteSeer
• J. G. Dyer, M. Lindemann, R. Perez, R. Sailer, L. van Doorn, S. W. Smith, and S. Weingart. Building the IBM 4758 secure coprocessor. IEEE Computer, 34(10):57--66, October 2001. CiteSeer