Associate Professor of Electrical and Computer Engineering
Office: 368 Durham Center
Phone: (515) 294-7940
Fax: (515) 294-1152
2215 Coover Hall
Department of Electrical and Computer Engineering
Iowa State University
Ames, IA 50011
Google scholar page.
My research interests include high performance computer architecture,
parallel and distributed computing, and architectural support for
security. Here is the full
My representative works include (not exclusively, and done with my
students and/or collaborators):
- "A permutation-based page interleaving scheme to reduce row-buffer
conflicts and exploit data locality" (MICRO 2000): We find out that
cache misses and writebacks may incur severe DRAM row-buffer conflicts
under conventional memory address mapping, and propose a simple
XOR-based mapping to resolve the conflicts.
The technique has been adopted in many processors and chipsets: Sun
UltraSPARC IIIi Sun Gemini, AMD Geode LX, AMD Geode GX3, Mobile Intel
4 Express chipset family, and NVIDIA chipset GeForce 7025/nForce 630a.
- "Thermal modeling and management of DRAM memory systems" (ISCA
2007), and "Software thermal management of DRAM memory for multicore
systems" (SIGMETRICS 2008): We propose a DRAM thermal model and two
software DRAM DTM (dynamic thermal management) methods, and then
demostrate the effectiveness of those methods on multicore computer
- "Gaining insights into multicore cache partitioning: bridging the
gap between simulation and real systems" (HPCA 2008). It is a
comprehensive execution- and measurement-based study on multicore
cache partitioning. The cache management method it proposes has been
been used in Linux kernel for production systems (See
- "Mini-Rank: Adaptive DRAM architecture for improving memory power
efficiency" (MICRO 2008): It demonstrates that reducing memory rank
size may significantly reduce memory power consumption.
- "Decoupled DIMM: building high-bandwidth Memory system from low-speed
DRAM devices" (ISCA 2009): It presents a technique to boost memory
bandwidth without increasing memory device frequency.
- "E3CC: A memory error protection scheme with novel address mapping
for sub-ranked and low-power memories" (TACO, to appear): It proposes
to use a novel address mapping scheme so that a non-ECC
memory DIMM may be used as an ECC memory DIMM.
Program co-chair, architecture track, The 8th IEEE International Conference on
Networking, Architecture, and Storage
(NAS 2013), Xi’an,
Shaanxi, China, July 10-12, 2013.
- Editorial board,
Parallel and Distributed Computing and Networks,