Chris Chu's Publications

Book Chapters:

• Natarajan Viswanathan, Min Pan and Chris Chu. FastPlace: An Efficient Multilevel Force-Directed Placement Algorithm. In Modern Circuit Placement: Best Practices and Results, Gi-Joon Nam and Jason Cong, Editors, Springer, 2007.
• Chris Chu and Min Pan. Clock Network Design: Basics. In The Handbook of Algorithms for VLSI Physical Design Automation, Chuck Alpert, Dinesh Mehta and Sachin Sapatnekar, Editors, CRC Press, pages 881-896, 2008.
• Chris Chu and Min Pan. Practical Issues in Clock Network Design. In The Handbook of Algorithms for VLSI Physical Design Automation, Chuck Alpert, Dinesh Mehta and Sachin Sapatnekar, Editors, CRC Press, pages 897-912, 2008.
• Chris Chu. Wire Sizing for VLSI Circuits. In Encyclopedia of Algorithms, Ming-Yang Kao, Editor, Springer, 2008.
• Chris Chu. Chapter 11: Placement. In Electronic Design Automation: Synthesis, Verification, and Test, Laung-Terng (L.-T.) Wang, Yao-Wen Chang and Kwang-Ting (Tim) Cheng, Editors, Elsevier, 2009.

Journal Articles:

• M. Y. Chan, F. Chin, C. N. Chu and W. K. Mak. Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. Journal of Parallel and Distributed Computing, vol. 33, no. 1, pages 98-106, February 1996.
• Chris C. N. Chu and D. F. Wong. A Matrix Synthesis Approach to Thermal Placement. IEEE Transactions on Computer-Aided Design, vol. 17, no. 11, pages 1166-1174, November 1998.
• Chris C. N. Chu and D. F. Wong. Greedy Wire-Sizing is Linear Time. IEEE Transactions on Computer-Aided Design, vol. 18, no. 4, pages 398-405, April 1999.
• F. Y. Young, Chris C. N. Chu and D. F. Wong. Generation of Universal Series-Parallel Boolean Functions. Journal of the ACM, vol. 46, no. 3, pages 416-435, May 1999.
• Chris C. N. Chu and D. F. Wong. A Quadratic Programming Approach to Simultaneous Buffer Insertion/Sizing and Wire Sizing. IEEE Transactions on Computer-Aided Design, vol. 18, no. 6, pages 787-798, June 1999. (TCAD Best Paper Award)
• Chung-Ping Chen, Chris C. N. Chu and D. F. Wong. Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation. IEEE Transactions on Computer-Aided Design, vol. 18, no. 7, pages 1014-1025, July 1999.
• Chris C. N. Chu and D. F. Wong. An Efficient and Optimal Algorithm for Simultaneous Buffer and Wire Sizing. IEEE Transactions on Computer-Aided Design, vol. 18, no. 9, pages 1297-1304, September 1999.
• Chris Chu and D. F. Wong. Closed Form Solution to Simultaneous Buffer Insertion / Sizing and Wire Sizing. ACM Transactions on Design Automation of Electronic Systems, vol. 6, no. 3, pages 343-371, July 2001.
• Yu-Yen Mo and Chris Chu A Hybrid Dynamic / Quadratic Programming Algorithm for Interconnect Tree Optimization. IEEE Transactions on Computer-Aided Design, vol. 20, no. 5, pages 680-686, May 2001.
• F. Y. Young, Chris C. N. Chu, W. S. Luk and Y. C. Wong. Handling Soft Modules in General Non-slicing Floorplan using Lagrangian Relaxation. IEEE Transactions on Computer-Aided Design, vol. 20, no. 5, pages 687-692, May 2001.
• Chris Chu and D. F. Wong. VLSI Circuit Performance Optimization by Geometric Programming. Annals of Operations Research, vol. 105, pages 37-60, July 2001.
• F. Y. Young, Chris C. N. Chu, and Zion Cien Shen. Twin Binary Sequences: A Non-redundant Representation for General Non-Slicing Floorplan. IEEE Transactions on Computer-Aided Design, vol. 22, no. 4, pages 457-469, April 2003.
• Cien Shen and Chris Chu. Bounds on the Number of Slicing, Mosaic and General Floorplans. IEEE Transactions on Computer-Aided Design, vol. 22, no. 10, pages 1354-1361, October 2003.
• D. Berleant, M.-P. Cheong, C. Chu, Y. Guan, A. Kamal, G. Sheblé, S. Ferson and J.F. Peters. Dependable Handling of Uncertainty. Reliable Computing, vol. 9, no. 6, pages 407-418, 2003.
• Chris C. N. Chu and Evangeline F. Y. Young. Non-Rectangular Shaping and Sizing of Soft Modules for Floorplan Design Improvement. IEEE Transactions on Computer-Aided Design, vol. 23, no. 1, pages 71-79, January 2004.
• Charles Alpert, Chris Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli Kashyap and Stephen Quay. Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique. IEEE Transactions on Computer-Aided Design, vol. 23, no. 1, pages 136-141, January 2004.
• Arif Abou-Seido, Brian Nowak and Chris Chu. Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. IEEE Transactions on VLSI Systems, vol. 12, no. 7, pages 691-696, July 2004.
• Evangeline F. Y. Young, Chris C. N. Chu and M. L. Ho. Placement Constraints in Floorplan Design. IEEE Transactions on VLSI Systems, vol. 12, no. 7, pages 735-745, July 2004.
• Sampath Dechu, Zion Cien Shen and Chris Chu. An Efficient Routing Tree Construction Algorithm with Buffer Insertion, Wire Sizing and Obstacle Considerations. IEEE Transactions on Computer-Aided Design, vol. 24, no. 4, pages 600-608, April 2005.
• Natarajan Viswanathan and Chris Chu. FastPlace: Efficient Analytical Placement using Cell Spreading, Iterative Local Refinement and a Hybrid Net Model. IEEE Transactions on Computer-Aided Design, vol. 24, no. 5, pages 722-733, May 2005.
• W. Zou, Chris Chu, S.M. Reddy and I. Pomeranz. Optimizing SOC Test Resources using Dual Sequences. In VLSI-SOC: From Systems to Chips, M. Glesner, R. Reis, L. Indrusiak, V. Mooney, and H. Eveking, Editors, Springer, 2006.
• Dennis K.Y. Tong, Evangeline F.Y. Young, Chris Chu and Sampath Dechu, Wire Retiming Problem with Net Topology Optimization. IEEE Transactions on Computer-Aided Design, vol. 26, no. 9, pages 1648-1669, September 2007.
• Chris Chu and Yiu-Chung Wong, FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. IEEE Transactions on Computer-Aided Design, vol. 27, no. 1, pages 70-83, January 2008.

Conference Papers:

• M. Y. Chan, F. Chin, C. N. Chu and W. K. Mak. Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. In Proc. 5th IEEE Symposium on Parallel and Distributed Processing, pages 285-288, 1993.
• Chris C. N. Chu and D. F. Wong. A Matrix Synthesis Approach to Thermal Placement. In Proc. Intl. Symp. on Physical Design, pages 163-168, 1997.
• Chris C. N. Chu and D. F. Wong. Closed Form Solution to Simultaneous Buffer Insertion/Sizing and Wire Sizing. In Proc. Intl. Symp. on Physical Design, pages 192-197, 1997.
• Chris C. N. Chu and D. F. Wong. A New Approach to Simultaneous Buffer Insertion and Wire Sizing. In Proc. IEEE Intl. Conf. on Computer-Aided Design, pages 614-621, 1997.
• Chris C. N. Chu and D. F. Wong. A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. In Proc. Conf. on Design Automation and Test in Europe, pages 479-485, 1998.
• Chris C. N. Chu and D. F. Wong. Greedy Wire-Sizing is Linear Time. In Proc. Intl. Symp. on Physical Design, pages 39-44, 1998.
• Chung-Ping Chen, Chris C. N. Chu and D. F. Wong. Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation. In Proc. IEEE Intl. Conf. on Computer-Aided Design, pages 617-624, 1998.
• Yu-Yen Mo and Chris C. N. Chu. A Hybrid Dynamic / Quadratic Programming Algorithm for Interconnect Tree Optimization. In Proc. Intl. Symp. on Physical Design, pages 134-139, 2000.
• F.Y. Young, Chris C. N. Chu, W.S. Luk and Y.C. Wong. Floorplan Area Minimization using Lagrangian Relaxation. In Proc. Intl. Symp. on Physical Design, pages 174-179, 2000.
• Evangeline F.Y. Young, Chris C. N. Chu and M. L. Ho. A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. In Proc. Asian and South Pacific Design Automation Conf., pages 661-667, 2002.
• Chris C. N. Chu and Evangeline F.Y. Young. Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. In Proc. Conf. on Design Automation and Test in Europe, pages 1101, 2002.
• Chuck Alpert, Chris Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli Kashyap and Stephen Quay. Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique. In Proc. Intl. Symp. on Physical Design, pages 104-109, 2002.
• F.Y. Young, Chris C. N. Chu and Zion Cien Shen. Twin Binary Sequences: A Non-Redundant Representation for General Non-Slicing Floorplan. In Proc. Intl. Symp. on Physical Design, pages 196-201, 2002.
• Arif Ishaq Abou-Seido, Brian Nowak and Chris Chu. Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. In Proc. Intl. Conf. Computer Design, pages 422-427, 2002.
• Steve T. W. Lai, Evangeline F.Y. Young and Chris C. N. Chu. A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. In Proc. Conf. on Design Automation and Test in Europe, pages 856-861, 2003.
• Chris C. N. Chu, Evangeline F.Y. Young, Dennis K.Y. Tong and Sampath Dechu. Retiming with Interconnect and Gate Delay. In Proc. IEEE Intl. Conf. on Computer-Aided Design, pages 221-226, 2003.
• W. Zou, Chris Chu, S.M. Reddy and I. Pomeranz. Optimizing SOC Test Resources using Dual Sequences. In Proc. IFIP Intl. Conf. on Very Large Scale Integration, pages 180-185, 2003.
• Sampath Dechu, Zion Cien Shen and Chris Chu. An Efficient Routing Tree Construction Algorithm with Buffer Insertion, Wire Sizing and Obstacle Considerations. In Proc. Asian and South Pacific Design Automation Conference, pages 361-366, 2004.
• Cien Shen and Chris Chu. Accurate and Efficient Flow based Congestion Estimation in Floorplanning. In Proc. Asian and South Pacific Design Automation Conference, pages 671-676, 2004.
• Natarajan Viswanathan and Chris Chu. FastPlace: Efficient Analytical Placement using Cell Spreading, Iterative Local Refinement and a Hybrid Net Model. In Proc. Intl. Symp. on Physical Design, pages 26-33, 2004. (Best paper award)
• Debjit Sinha, Hai Zhou and Chris Chu. Optimal Gate Sizing for Coupling-Noise Reduction. In Proc. Intl. Symp. on Physical Design, pages 176-181, 2004.
• Chris Chu. FLUTE: Fast Lookup Table Based Wirelength Estimation Technique. In Proc. IEEE Intl. Conf. on Computer-Aided Design, pages 696-701, 2004.
• Min Pan, Chris Chong-Nuen Chu and J. Morris Chang, Transition Time Bounded Low-Power Clock Tree Construction. In Proc. IEEE Intl. Symp. Circuits and Systems, pages 2445-2448, 2005.
• Min Pan, Chris Chong-Nuen Chu and Hai Zhou, Timing Yield Estimation Using Statistical Static Timing Analysis. In Proc. IEEE Intl. Symp. Circuits and Systems, pages 2461-2464, 2005.
• Chris Chu and Yiu-Chung Wong, Fast and Accurate Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. In Proc. Intl. Symp. on Physical Design, pages 28-35, 2005.
• Natarajan Viswanathan, Min Pan and Chris Chu, FastPlace: An Analytical Placer for Mixed-Mode Designs. In Proc. Intl. Symp. on Physical Design, pages 221-223, 2005.
• Zion Shen, Chris C. N. Chu and Ying-Meng Li, Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. International Conference on Computer Design, pages 38-44, 2005.
• Natarajan Viswanathan, Min Pan and Chris Chong-Nuen Chu, An Efficient Analytical Placement Algorithm for Mixed-Mode Designs in the presence of Placement Blockages. SRC TECHCON Conference, 2005.
• Min Pan, Natarajan Viswanathan and Chris Chu, An Efficient and Effective Detailed Placement Algorithm. IEEE/ACM International Conference on Computer-Aided Design, pages 48-55, 2005.
• Natarajan Viswanathan, Min Pan and Chris Chong-Nuen Chu, An Efficient Analytical Placement Algorithm for Mixed-Mode Designs. Asian and South Pacific Design Automation Conference, pages 195-200, 2006.
• Chiu-wing Sham, Evangeline F. Y. Young and Chris Chu, Optimal Cell Flipping in Placement and Floorplanning. IEEE/ACM Design Automation Conference, pages 1109-1114, 2006.
• Min Pan and Chris Chu, FastRoute: A Step to Integrate Global Routing into Placement. IEEE/ACM International Conference on Computer-Aided Design, pages 464-471, 2006.
• Chuan Lin, Hai Zhou and Chris Chu, A Revisit to Floorplan Optimization by Lagrangian Relaxation. IEEE/ACM International Conference on Computer-Aided Design, pages 164-171, 2006.
• Royce L.S. Ching, Evangeline F.Y. Young, Kevin C.K. Leung, and Chris Chu, Post-Placement Voltage Island Generation. IEEE/ACM International Conference on Computer-Aided Design, pages 641-646, 2006.
• Y.C. Tam, Evangeline F.Y. Young and Chris Chu, Analog Placement with Symmetry and Other Placement Constraints. IEEE/ACM International Conference on Computer-Aided Design, pages 349-354, 2006.
• Min Pan, Chris Chu and Priyadarsan Patra, A Novel Performance-Driven Topology Design Algorithm. Asian and South Pacific Design Automation Conference, pages 244-249, 2007.
• Min Pan and Chris Chu, FastRoute 2.0: A High-quality and Efficient Global Router. Asian and South Pacific Design Automation Conference, pages 250-255, 2007.
• Natarajan Viswanathan, Min Pan and Chris Chu, FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. Asian and South Pacific Design Automation Conference, pages 135-140, 2007.
• Min Pan and Chris Chu, IPR: An Integrated Placement and Routing Algorithm. IEEE/ACM Design Automation Conference, pages 59-62, 2007.
• Natarajan Viswanathan, Gi-Joon Nam, Charles Alpert, Paul Villarrubia, Haoxing Ren and Chris Chu, RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. IEEE/ACM Design Automation Conference, pages 453-458, 2007.
• Charles J. Alpert, Chris Chu and Paul G. Villarrubia, Physical Synthesis Comes of Age. IEEE/ACM International Conference on Computer-Aided Design, pages 246-249, 2007.
• Yiu-Chung Wong and Chris Chu, A Scalable and Accurate Rectilinear Steiner Minimal Tree Algorithm. International Symposium on VLSI Design, Automation and Test, pages 29-34, 2008.
• Jackey Z. Yan and Chris Chu, DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanner. IEEE/ACM Design Automation Conference, pages 161-166, 2008.
• Yanheng Zhang, Yue Xu and Chris Chu, FastRoute 3.0: A Fast and High Quality Global Router Based on Virtual Capacity. IEEE/ACM International Conference on Computer-Aided Design, pages 344-349, 2008.
• Yue Xu, Yanheng Zhang and Chris Chu, FastRoute 4.0: Global Router with Efficient Via Minimization. Asian and South Pacific Design Automation Conference, pages 576 - 581, 2009.
• Hua Xiang, Chris Chu and Ruchir Puri, A Simple Fast Exact Density Calculation Algorithm. IEEE International Conference on Integrated Circuit Design and Technology, 2009.
• Jackey Z. Yan, Natarajan Viswanathan and Chris Chu, Handling Complexities in Modern Large-Scale Mixed-Size Placement. IEEE/ACM Design Automation Conference, 2009.
• Yu-Chen Lin, Wai-Kei Mak, Chris Chu and Ting-Chi Wang, Pad Assignment for Die-Stacking System-in-Package Design. IEEE/ACM International Conference on Computer-Aided Design, pages 249-255, 2009.
• Yue Xu and Chris Chu, GREMA: Graph Reduction Based Efficient Mask Assignment for Double Patterning Technology. IEEE/ACM International Conference on Computer-Aided Design, pages 601-606, 2009.
• Yanheng Zhang and Chris Chu, CROP: Fast and Effective Congestion Refinement of Placement. IEEE/ACM International Conference on Computer-Aided Design, pages 344-350, 2009.

Technical Reports:

• Chris C. N. Chu, Chung-Ping Chen and D. F. Wong. Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation. Department of Computer Science, University of Texas at Austin, TR98-06, February, 1998.

Dissertation:

• Chong-Nuen Chu, "Efficient and Optimal Solutions for Interconnect Optimization", Ph.D. Dissertation, The University of Texas at Austin, August 1999.